1. Technical Field
The present invention generally relates to phase locked loops and in particular to feedback circuits in phase-locked loop circuits.
2. Description of the Related Art
High speed serializers/deserializers (serdes) implement phased locked loops (PLLs) to frequency multiply an input reference clock to a frequency suitable for clocking transmitter and receiver functions. Often, PLLs utilized to frequency multiply should deliver low phase error, thereby multiple PLLs clocked from one reference clock will produce phase aligned output clocks relative to one another. The phase alignment of the output clocks allow multiple cores to be synchronized. An important aspect of PLL design is to keep potential sources of static phase offset as low as possible, thereby keeping the PLL phase error low. When PLLs are required to produce multiple output phases, maintaining low duty cycle distortion is also advantageous.
Many times the charge pump of a PLL is a significant source of phase offset. Differential charge pumps configure in a switched bridge topology are particularly vulnerable to device mismatch due to the charge pump's common-mode feedback. The common-mode feedback may not null out static error due to differences between the differential legs (creating a differential voltage). Properly designed single-ended charge pumps may yield very low static offsets, however many voltage controlled oscillators (VCOs) implement differential control voltage inputs.